// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  hipciec_ap_iob_rx_com_reg_reg_offset.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2017/10/24
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/16 18:03:15 Create file
// ******************************************************************************

#ifndef __HIPCIEC_AP_IOB_RX_COM_REG_REG_OFFSET_H__
#define __HIPCIEC_AP_IOB_RX_COM_REG_REG_OFFSET_H__

/* HIPCIEC_AP_IOB_RX_COM_REG Base address of Module's Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE                       (0x4000)

/******************************************************************************/
/*                      HiPCIECTRL40V200 HIPCIEC_AP_IOB_RX_COM_REG Registers' Definitions                            */
/******************************************************************************/

#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_0_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x0)    /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_1_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x20)   /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_2_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x40)   /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_3_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x60)   /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_4_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x80)   /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_5_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA0)   /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_6_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xC0)   /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_7_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xE0)   /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_8_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x100)  /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_9_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x120)  /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_10_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x140)  /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_11_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x160)  /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_12_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x180)  /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_13_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A0)  /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_14_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C0)  /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_15_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E0)  /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_16_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x200)  /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_17_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x220)  /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_18_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x240)  /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_19_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x260)  /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_20_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x280)  /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_21_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2A0)  /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_22_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2C0)  /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_23_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2E0)  /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_24_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x300)  /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_25_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x320)  /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_26_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x340)  /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_27_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x360)  /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_28_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x380)  /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_29_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3A0)  /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_30_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3C0)  /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_31_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3E0)  /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_32_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x400)  /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_33_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x420)  /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_0_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x4)    /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_1_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x24)   /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_2_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x44)   /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_3_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x64)   /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_4_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x84)   /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_5_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA4)   /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_6_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xC4)   /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_7_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xE4)   /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_8_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x104)  /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_9_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x124)  /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_10_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x144)  /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_11_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x164)  /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_12_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x184)  /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_13_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A4)  /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_14_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C4)  /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_15_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E4)  /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_16_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x204)  /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_17_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x224)  /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_18_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x244)  /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_19_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x264)  /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_20_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x284)  /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_21_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2A4)  /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_22_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2C4)  /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_23_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2E4)  /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_24_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x304)  /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_25_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x324)  /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_26_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x344)  /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_27_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x364)  /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_28_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x384)  /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_29_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3A4)  /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_30_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3C4)  /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_31_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3E4)  /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_32_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x404)  /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_33_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x424)  /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_0_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x8)    /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_1_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x28)   /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_2_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x48)   /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_3_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x68)   /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_4_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x88)   /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_5_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA8)   /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_6_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xC8)   /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_7_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xE8)   /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_8_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x108)  /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_9_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x128)  /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_10_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x148)  /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_11_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x168)  /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_12_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x188)  /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_13_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A8)  /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_14_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C8)  /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_15_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E8)  /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_16_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x208)  /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_17_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x228)  /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_18_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x248)  /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_19_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x268)  /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_20_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x288)  /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_21_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2A8)  /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_22_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2C8)  /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_23_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2E8)  /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_24_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x308)  /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_25_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x328)  /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_26_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x348)  /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_27_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x368)  /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_28_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x388)  /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_29_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3A8)  /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_30_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3C8)  /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_31_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3E8)  /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_32_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x408)  /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_33_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x428)  /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_0_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xC)    /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_1_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2C)   /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_2_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x4C)   /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_3_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x6C)   /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_4_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x8C)   /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_5_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAC)   /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_6_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xCC)   /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_7_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xEC)   /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_8_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10C)  /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_9_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12C)  /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_10_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x14C)  /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_11_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x16C)  /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_12_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18C)  /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_13_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1AC)  /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_14_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1CC)  /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_15_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1EC)  /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_16_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x20C)  /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_17_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x22C)  /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_18_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x24C)  /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_19_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x26C)  /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_20_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x28C)  /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_21_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2AC)  /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_22_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2CC)  /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_23_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2EC)  /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_24_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x30C)  /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_25_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x32C)  /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_26_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x34C)  /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_27_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x36C)  /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_28_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x38C)  /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_29_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3AC)  /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_30_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3CC)  /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_31_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3EC)  /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_32_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x40C)  /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_33_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x42C)  /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_0_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10)   /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_1_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x30)   /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_2_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x50)   /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_3_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x70)   /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_4_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x90)   /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_5_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xB0)   /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_6_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xD0)   /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_7_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xF0)   /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_8_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x110)  /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_9_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x130)  /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_10_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x150)  /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_11_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x170)  /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_12_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x190)  /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_13_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B0)  /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_14_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1D0)  /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_15_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F0)  /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_16_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x210)  /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_17_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x230)  /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_18_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x250)  /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_19_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x270)  /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_20_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x290)  /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_21_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2B0)  /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_22_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2D0)  /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_23_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2F0)  /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_24_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x310)  /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_25_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x330)  /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_26_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x350)  /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_27_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x370)  /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_28_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x390)  /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_29_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3B0)  /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_30_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3D0)  /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_31_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3F0)  /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_32_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x410)  /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_33_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x430)  /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_0_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x14)   /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_1_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x34)   /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_2_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x54)   /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_3_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x74)   /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_4_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x94)   /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_5_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xB4)   /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_6_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xD4)   /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_7_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xF4)   /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_8_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x114)  /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_9_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x134)  /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_10_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x154)  /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_11_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x174)  /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_12_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x194)  /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_13_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B4)  /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_14_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1D4)  /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_15_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F4)  /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_16_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x214)  /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_17_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x234)  /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_18_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x254)  /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_19_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x274)  /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_20_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x294)  /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_21_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2B4)  /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_22_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2D4)  /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_23_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2F4)  /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_24_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x314)  /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_25_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x334)  /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_26_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x354)  /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_27_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x374)  /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_28_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x394)  /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_29_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3B4)  /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_30_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3D4)  /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_31_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3F4)  /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_32_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x414)  /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_33_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x434)  /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_0_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18)   /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_1_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x38)   /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_2_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x58)   /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_3_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x78)   /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_4_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x98)   /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_5_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xB8)   /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_6_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xD8)   /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_7_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xF8)   /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_8_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x118)  /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_9_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x138)  /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_10_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x158)  /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_11_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x178)  /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_12_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x198)  /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_13_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B8)  /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_14_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1D8)  /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_15_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F8)  /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_16_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x218)  /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_17_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x238)  /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_18_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x258)  /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_19_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x278)  /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_20_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x298)  /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_21_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2B8)  /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_22_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2D8)  /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_23_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2F8)  /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_24_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x318)  /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_25_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x338)  /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_26_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x358)  /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_27_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x378)  /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_28_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x398)  /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_29_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3B8)  /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_30_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3D8)  /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_31_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3F8)  /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_32_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x418)  /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_33_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x438)  /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_0_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C)   /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_1_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3C)   /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_2_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x5C)   /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_3_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x7C)   /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_4_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x9C)   /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_5_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xBC)   /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_6_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xDC)   /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_7_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xFC)   /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_8_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11C)  /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_9_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x13C)  /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_10_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15C)  /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_11_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x17C)  /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_12_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x19C)  /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_13_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1BC)  /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_14_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1DC)  /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_15_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1FC)  /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_16_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x21C)  /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_17_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23C)  /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_18_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x25C)  /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_19_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x27C)  /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_20_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x29C)  /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_21_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2BC)  /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_22_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2DC)  /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_23_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2FC)  /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_24_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x31C)  /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_25_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x33C)  /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_26_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x35C)  /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_27_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x37C)  /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_28_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x39C)  /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_29_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3BC)  /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_30_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3DC)  /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_31_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3FC)  /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_32_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x41C)  /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_33_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x43C)  /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_CNT_CLR_CE_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA00)  /* counter type control register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_0_REG                                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA40)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_1_REG                                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA44)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_2_REG                                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA48)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_3_REG                                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA4C)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_4_REG                                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA50)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_5_REG                                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA54)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_6_REG                                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA58)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_7_REG                                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA5C)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_8_REG                                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA60)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_9_REG                                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA64)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_10_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA68)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_11_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA6C)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_12_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA70)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_13_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA74)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_14_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA78)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_15_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA7C)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_16_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA80)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_17_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA84)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_18_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA88)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_19_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA8C)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_20_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA90)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_21_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA94)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_22_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA98)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_23_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA9C)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_24_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAA0)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_25_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAA4)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_26_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAA8)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_27_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAAC)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_28_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAB0)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_29_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAB4)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_30_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAB8)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_31_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xABC)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_32_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAC0)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_33_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAC4)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_34_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAC8)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_35_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xACC)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_36_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAD0)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_37_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAD4)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_38_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAD8)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_39_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xADC)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_40_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAE0)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_41_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAE4)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_42_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAE8)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_43_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAEC)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_44_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAF0)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_45_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAF4)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_46_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAF8)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_47_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAFC)  /* IOB RX tlp counter. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_PREFIX_STS_0_REG                              (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xB00)  /* IOB RX C0 received prefix state */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_PREFIX_STS_1_REG                              (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xB04)  /* IOB RX C1 received prefix state */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_PREFIX_STS_2_REG                              (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xB08)  /* IOB RX C2 received prefix state */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_APAT_TLB_PREDICTOR_HINT_CFG_REG                      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1140) /* Hint generated config */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_APAT_TLB_PREDICTOR_FIFO_DFX_REG                      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1144) /* TLB predictor FIFO DFx */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_APAT_TLB_PREDICTOR_PAGE_SIZE_CACHE_PERFORMANCE_0_REG (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1148) /* 16KB/64KB/2MB page size cache hit and miss ratio */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_APAT_TLB_PREDICTOR_PAGE_SIZE_CACHE_PERFORMANCE_1_REG (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x114C) /* 16KB/64KB/2MB page size cache evict and not_replace ratio */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_APAT_TLB_PREDICTOR_LOCK_CACHE_PERFORMANCE_0_REG      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1150) /* LOCK hint cache hit and miss ratio */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_APAT_TLB_PREDICTOR_LOCK_CACHE_PERFORMANCE_1_REG      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1154) /* LOCK hint cache evict and not_replace ratio */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_APAT_TLB_PREDICTOR_RAM_PARITY_DFX_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1158) /* RAM parity check DFX */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_APAT_XILINX_HOOK_PASID_CFG_0_REG                     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1190) /* APAT ATS PASID config #0 for Xilinx Hook Test */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_APAT_XILINX_HOOK_PASID_CFG_1_REG                     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1194) /* APAT ATS PASID config #1 for Xilinx Hook Test */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_APAT_XILINX_HOOK_PASID_CFG_2_REG                     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1198) /* APAT ATS PASID config #2 for Xilinx Hook Test */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_APAT_XILINX_HOOK_PASID_CFG_3_REG                     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x119C) /* APAT ATS PASID config #3 for Xilinx Hook Test */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_APAT_XILINX_HOOK_PASID_CFG_4_REG                     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11A0) /* priv/exec bit config #0 for Xilinx Hook Test */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_APAT_XILINX_HOOK_PASID_CFG_5_REG                     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11A4) /* priv/exec bit config #1 for Xilinx Hook Test */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_APAT_XILINX_HOOK_PASID_CFG_6_REG                     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11A8) /* priv/exec bit config #2 for Xilinx Hook Test */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_APAT_XILINX_HOOK_PASID_CFG_7_REG                     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11AC) /* priv/exec bit config #3 for Xilinx Hook Test */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_0_REG                               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1500) /* MSI/MSIX control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_1_REG                               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1510) /* MSI/MSIX control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_2_REG                               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1520) /* MSI/MSIX control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_3_REG                               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1530) /* MSI/MSIX control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_4_REG                               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1540) /* MSI/MSIX control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_5_REG                               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1550) /* MSI/MSIX control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_6_REG                               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1560) /* MSI/MSIX control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_7_REG                               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1570) /* MSI/MSIX control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_8_REG                               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1580) /* MSI/MSIX control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_9_REG                               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1590) /* MSI/MSIX control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_10_REG                              (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15A0) /* MSI/MSIX control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_11_REG                              (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15B0) /* MSI/MSIX control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_12_REG                              (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15C0) /* MSI/MSIX control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_13_REG                              (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15D0) /* MSI/MSIX control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_14_REG                              (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15E0) /* MSI/MSIX control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_0_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1504) /* MSI/MSIX address high 32bits */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_1_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1514) /* MSI/MSIX address high 32bits */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_2_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1524) /* MSI/MSIX address high 32bits */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_3_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1534) /* MSI/MSIX address high 32bits */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_4_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1544) /* MSI/MSIX address high 32bits */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_5_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1554) /* MSI/MSIX address high 32bits */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_6_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1564) /* MSI/MSIX address high 32bits */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_7_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1574) /* MSI/MSIX address high 32bits */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_8_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1584) /* MSI/MSIX address high 32bits */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_9_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1594) /* MSI/MSIX address high 32bits */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_10_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15A4) /* MSI/MSIX address high 32bits */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_11_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15B4) /* MSI/MSIX address high 32bits */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_12_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15C4) /* MSI/MSIX address high 32bits */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_13_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15D4) /* MSI/MSIX address high 32bits */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_14_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15E4) /* MSI/MSIX address high 32bits */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_0_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1508) /* MSI/MSIX address low 32bits */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_1_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1518) /* MSI/MSIX address low 32bits */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_2_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1528) /* MSI/MSIX address low 32bits */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_3_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1538) /* MSI/MSIX address low 32bits */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_4_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1548) /* MSI/MSIX address low 32bits */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_5_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1558) /* MSI/MSIX address low 32bits */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_6_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1568) /* MSI/MSIX address low 32bits */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_7_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1578) /* MSI/MSIX address low 32bits */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_8_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1588) /* MSI/MSIX address low 32bits */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_9_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1598) /* MSI/MSIX address low 32bits */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_10_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15A8) /* MSI/MSIX address low 32bits */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_11_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15B8) /* MSI/MSIX address low 32bits */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_12_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15C8) /* MSI/MSIX address low 32bits */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_13_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15D8) /* MSI/MSIX address low 32bits */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_14_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15E8) /* MSI/MSIX address low 32bits */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_NVME_CFG_REMAP_CTRL_REG                              (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15F0) /* NVME cfg address remap ctrl */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_RX_COM_ECO_REG_0_REG                                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15F4) 
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_RX_COM_ECO_REG_1_REG                                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15F8) 
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_PROT_MODE_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1600) /* MSI/MSIX operation protection mode */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_SMMU_BYPASS_PORT_EN_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1800) /* smmu bypass enable for each port configuration register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_ATOP_ENDIAN_FORMAT_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1804) /* Endian Format Control of inbound atomic operation */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_ATU_ABORT_MODE_REG                                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1808) /* Completion statues configuration of ATU match fail request */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_TLP_FILTER_REG                                    (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x180C) /* Inbound TLP filter control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_SMMU_SYNC_TO_REG                              (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1810) /* SMMU SYNC timeout control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_NP_DELAY_CTRL_0_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1940) /* IOB RX NPR delay control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_NP_DELAY_CTRL_1_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1944) /* IOB RX NPR delay control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_NP_DELAY_CTRL_2_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1948) /* IOB RX NPR delay control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_P_DELAY_CTRL_0_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1950) /* IOB RX PR delay control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_P_DELAY_CTRL_1_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1954) /* IOB RX PR delay control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_P_DELAY_CTRL_2_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1958) /* IOB RX PR delay control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_CPL_DELAY_CTRL_0_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1960) /* IOB RX CPL delay control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_CPL_DELAY_CTRL_1_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1964) /* IOB RX CPL delay control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_CPL_DELAY_CTRL_2_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1968) /* IOB RX CPL delay control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF64_SPACE_MR_DST_LOW_L_0_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A00) /* memory range for destination 0~destination3 of Prefetchable 64bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF64_SPACE_MR_DST_LOW_L_1_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B00) /* memory range for destination 0~destination3 of Prefetchable 64bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF64_SPACE_MR_DST_LOW_L_2_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C00) /* memory range for destination 0~destination3 of Prefetchable 64bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF64_SPACE_MR_DST_LOW_L_3_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1D00) /* memory range for destination 0~destination3 of Prefetchable 64bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF64_SPACE_MR_DST_LOW_H_0_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A04) /* memory range for destination 0~destination3 of Prefetchable 64bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF64_SPACE_MR_DST_LOW_H_1_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B04) /* memory range for destination 0~destination3 of Prefetchable 64bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF64_SPACE_MR_DST_LOW_H_2_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C04) /* memory range for destination 0~destination3 of Prefetchable 64bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF64_SPACE_MR_DST_LOW_H_3_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1D04) /* memory range for destination 0~destination3 of Prefetchable 64bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF64_SPACE_MR_DST_HIGH_L_0_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A08) /* memory range for destination 0~destination3 of Prefetchable 64bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF64_SPACE_MR_DST_HIGH_L_1_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B08) /* memory range for destination 0~destination3 of Prefetchable 64bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF64_SPACE_MR_DST_HIGH_L_2_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C08) /* memory range for destination 0~destination3 of Prefetchable 64bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF64_SPACE_MR_DST_HIGH_L_3_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1D08) /* memory range for destination 0~destination3 of Prefetchable 64bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF64_SPACE_MR_DST_HIGH_H_0_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A0C) /* memory range for destination 0~destination3 of Prefetchable 64bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF64_SPACE_MR_DST_HIGH_H_1_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B0C) /* memory range for destination 0~destination3 of Prefetchable 64bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF64_SPACE_MR_DST_HIGH_H_2_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C0C) /* memory range for destination 0~destination3 of Prefetchable 64bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF64_SPACE_MR_DST_HIGH_H_3_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1D0C) /* memory range for destination 0~destination3 of Prefetchable 64bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF32_SPACE_MR_DST_LOW_L_0_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A10) /* memory range for destination 0~destination3 of Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF32_SPACE_MR_DST_LOW_L_1_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B10) /* memory range for destination 0~destination3 of Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF32_SPACE_MR_DST_LOW_L_2_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C10) /* memory range for destination 0~destination3 of Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF32_SPACE_MR_DST_LOW_L_3_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1D10) /* memory range for destination 0~destination3 of Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF32_SPACE_MR_DST_LOW_H_0_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A14) /* memory range for destination 0~destination3 of Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF32_SPACE_MR_DST_LOW_H_1_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B14) /* memory range for destination 0~destination3 of Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF32_SPACE_MR_DST_LOW_H_2_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C14) /* memory range for destination 0~destination3 of Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF32_SPACE_MR_DST_LOW_H_3_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1D14) /* memory range for destination 0~destination3 of Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF32_SPACE_MR_DST_HIGH_L_0_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A18) /* memory range for destination 0~destination3 of Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF32_SPACE_MR_DST_HIGH_L_1_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B18) /* memory range for destination 0~destination3 of Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF32_SPACE_MR_DST_HIGH_L_2_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C18) /* memory range for destination 0~destination3 of Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF32_SPACE_MR_DST_HIGH_L_3_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1D18) /* memory range for destination 0~destination3 of Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF32_SPACE_MR_DST_HIGH_H_0_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A1C) /* memory range for destination 0~destination3 of Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF32_SPACE_MR_DST_HIGH_H_1_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B1C) /* memory range for destination 0~destination3 of Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF32_SPACE_MR_DST_HIGH_H_2_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C1C) /* memory range for destination 0~destination3 of Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_PF32_SPACE_MR_DST_HIGH_H_3_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1D1C) /* memory range for destination 0~destination3 of Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_NPF32_SPACE_MR_DST_LOW_L_0_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A20) /* memory range for destination 0~destination3 of non-Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_NPF32_SPACE_MR_DST_LOW_L_1_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B20) /* memory range for destination 0~destination3 of non-Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_NPF32_SPACE_MR_DST_LOW_L_2_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C20) /* memory range for destination 0~destination3 of non-Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_NPF32_SPACE_MR_DST_LOW_L_3_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1D20) /* memory range for destination 0~destination3 of non-Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_NPF32_SPACE_MR_DST_LOW_H_0_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A24) /* memory range for destination 0~destination3 of non-Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_NPF32_SPACE_MR_DST_LOW_H_1_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B24) /* memory range for destination 0~destination3 of non-Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_NPF32_SPACE_MR_DST_LOW_H_2_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C24) /* memory range for destination 0~destination3 of non-Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_NPF32_SPACE_MR_DST_LOW_H_3_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1D24) /* memory range for destination 0~destination3 of non-Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_NPF32_SPACE_MR_DST_HIGH_L_0_REG               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A28) /* memory range for destination 0~destination3 of non-Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_NPF32_SPACE_MR_DST_HIGH_L_1_REG               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B28) /* memory range for destination 0~destination3 of non-Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_NPF32_SPACE_MR_DST_HIGH_L_2_REG               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C28) /* memory range for destination 0~destination3 of non-Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_NPF32_SPACE_MR_DST_HIGH_L_3_REG               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1D28) /* memory range for destination 0~destination3 of non-Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_NPF32_SPACE_MR_DST_HIGH_H_0_REG               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A2C) /* memory range for destination 0~destination3 of non-Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_NPF32_SPACE_MR_DST_HIGH_H_1_REG               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B2C) /* memory range for destination 0~destination3 of non-Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_NPF32_SPACE_MR_DST_HIGH_H_2_REG               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C2C) /* memory range for destination 0~destination3 of non-Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_NPF32_SPACE_MR_DST_HIGH_H_3_REG               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1D2C) /* memory range for destination 0~destination3 of non-Prefetchable 32bit memory address space */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_BR_DST_0_REG                                  (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A30) /* For the inbound completion and message, uses the host bridge bus range to determine the target Peer2Peer host bridge */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_BR_DST_1_REG                                  (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B30) /* For the inbound completion and message, uses the host bridge bus range to determine the target Peer2Peer host bridge */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_BR_DST_2_REG                                  (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C30) /* For the inbound completion and message, uses the host bridge bus range to determine the target Peer2Peer host bridge */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_BR_DST_3_REG                                  (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1D30) /* For the inbound completion and message, uses the host bridge bus range to determine the target Peer2Peer host bridge */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_DEST_ADDR_0_REG                               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A34) /* P2P Destiantion id route address[47:16] configuration */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_DEST_ADDR_1_REG                               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B34) /* P2P Destiantion id route address[47:16] configuration */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_DEST_ADDR_2_REG                               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C34) /* P2P Destiantion id route address[47:16] configuration */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_DEST_ADDR_3_REG                               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1D34) /* P2P Destiantion id route address[47:16] configuration */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_ROUTE_CONTROL_0_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A38) /* P2P Route control register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_ROUTE_CONTROL_1_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B38) /* P2P Route control register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_ROUTE_CONTROL_2_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C38) /* P2P Route control register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_ROUTE_CONTROL_3_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1D38) /* P2P Route control register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_CREDIT_CURRENT_0_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A3C) /* P2P Destiantion id route latency statistic */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_CREDIT_CURRENT_1_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B3C) /* P2P Destiantion id route latency statistic */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_CREDIT_CURRENT_2_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C3C) /* P2P Destiantion id route latency statistic */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_CREDIT_CURRENT_3_REG                          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1D3C) /* P2P Destiantion id route latency statistic */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_DEST_LATENCY_AVERAGE_0_REG                    (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A40) /* P2P Destiantion id route latency statistic */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_DEST_LATENCY_AVERAGE_1_REG                    (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B40) /* P2P Destiantion id route latency statistic */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_DEST_LATENCY_AVERAGE_2_REG                    (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C40) /* P2P Destiantion id route latency statistic */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_DEST_LATENCY_AVERAGE_3_REG                    (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1D40) /* P2P Destiantion id route latency statistic */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_CFG_STAT_AVERAGE_NUM_REG                      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E00) /* average time configuration for P2P Destiantion id route latency statistic */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_CREDIT_ADJUST_GAP_REG                         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E04) /* P2P credit adjust control register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_CREDIT_ADJUST_STEP_REG                        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E08) /* P2P credit adjust control register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_STASH_TBL_RD_REG                              (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F00) /* tph stash table read */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_STASH_TBL_WR_REG                              (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F04) /* tph stash table write */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_STASH_TBL_STIDX_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F08) /* stash table r/w stdix */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_STASH_TBL_WDATA_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F0C) /* stash tabel write data */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_STASH_TBL_RDATA_REG                           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F10) /* stash table read data */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_REPLACE_CTRL_0_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F20) /* tph replace control for each request port */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_REPLACE_CTRL_1_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F24) /* tph replace control for each request port */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_REPLACE_CTRL_2_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F28) /* tph replace control for each request port */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_REPLACE_CTRL_3_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F2C) /* tph replace control for each request port */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_REPLACE_CTRL_4_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F30) /* tph replace control for each request port */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_REPLACE_CTRL_5_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F34) /* tph replace control for each request port */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_REPLACE_CTRL_6_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F38) /* tph replace control for each request port */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_REPLACE_CTRL_7_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F3C) /* tph replace control for each request port */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_REPLACE_CTRL_8_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F40) /* tph replace control for each request port */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_REPLACE_CTRL_9_REG                            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F44) /* tph replace control for each request port */

#endif // __HIPCIEC_AP_IOB_RX_COM_REG_REG_OFFSET_H__
